In my head, a 6 inputs lookup table is "by definition" a 64 -> 1 MUX, as for each combination of input bits you can define an output. (the 6 bits are then selection bits)....
It depends what the values connected to the muxes are.
If the values are all constant from a 6 bit select line, then yes.
If not, ie. you need to mux dynamic signals A,B,C,D, then the largest Mux you can implement with a 6 input lut is a 4-1. 2 input select lines and 4 variable inputs.
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I guess - in the strictest sense, you could argue that in fact, my 2nd option is really only the first one.
But from a more abstract circuit design POV, it's not a 64-> mux.
If not, ie. you need to mux dynamic signals A,B,C,D, then the largest Mux you can implement with a 6 input lut is a 4-1. 2 input select lines and 4 variable inputs.
process(a, b, c, d, sel_bits)
begin
mux_out <= a when sel_bits = "00" else
b when sel_bits = "01" else
c when sel_bits = "10" else
d when sel_bits = "11" else
'X';
end process
6 input bits and one output bit, perfect for one 6-input LUT.
I am not sure I understand what you want. A 6-input LUT is only a 64 x 1 bit RAM initialized to give the correct output. All 6 inputs are used as address lines.
The hardware inside the FPGA will be identical if you instantiate a ROM64X1 with the proper contents.
Do you want to see the memory contents?