Suitable metal layer for CLOCK signal in digital designs

Hi everybody

What is the suitable metal layer for CLOCK signal in large digital design (Transistor numbers>1000000)? and why?
Could you please introduce me a good reference describing such subjects?

Thanks

a.akbari61 said:

What is the suitable metal layer for CLOCK signal in large digital design (Transistor numbers>1000000)? and why?

Click to expand...

Actually any metal layer is suited. However, from a point of view regarding least parasitic capacitance and least series resistance, the top metal layer suits best (its disadvantage is: it always needs the highest count of vias down to the clock receiver).

a.akbari61 said:

Could you please introduce me a good reference describing such subjects?

Click to expand...

Below pls. find a page from the Weste/Harris book on "CMOS VLSI Design" on clock distribution.

a.akbari61 said:

Hi everybody

What is the suitable metal layer for CLOCK signal in large digital design (Transistor numbers>1000000)? and why?
Could you please introduce me a good reference describing such subjects?

Thanks

Click to expand...

Here is a good book on clock network design:


High-Speed Clock Network Design
Qing K. Zhu

https://www.amazon.com/High-Speed-C...=sr_1_1?ie=UTF8&s=books&qid=1271834471&sr=1-1