suggestions to the ADC architecture

[ycm]

adc architecture

for a 12 bit ADC, conversion time is around 1ms, input signal is very low frequency signal. what kind of ADC should be chosen considering the power, noise and die size? My understanding is I can chose either a SAR or integrating one, which one is better?

thanks.

 

[mikersia]

latest 2009 adc architecture

first order sigma-delta with first (reversive counter) or second order sinc2 decimator, IMHO

 

[ycm]

first order sigma-delta with first (reversive counter) or second order sinc2 decimator, IMHO

Hi Mikersia,

can you talk a little bit more about why sigma-delta is preferred for this case? thanks.

 

[yxo]

Be aware that sigma-delta includes very complicated math.

 

[mikersia]

sigma-delta is relatively simple and widely used; have integration nature, giving very high accuracy and noise suppression, what is important in practically all sensing aplications; have big flexibility in relation to programming of (resolution/conversion_time) by simple exchange of digital portion only; first and second order of sigma-delta (that enough for you case) are unconditionally stable and don't require time consuming stability investigations,- you have to provide choice of only some coefficients, guaranting absence of integrator saturation; ...