Thank you very much for all the responses!
I have been looking for FIFOs and one question appeared...Is it possible to have an asynchronous FIFO (as I have 2 clocks) that deals with Packets?
As I saw in FIFO generator datasheet, it should only be possible to transmit packets using synchronous FIFO...
Also, can anyone suggest me a way to test how it should work?
I mean, is there a way to Generate a Frame, pass it through FIFO or BRAM and then read it again, to understand the mechanism.
I would like to understand it first, and then incorporate to my top level.
Do I need to use ISIM, Chipscope or something like that?
Thanks!