rahdirs
Advanced Member level 1
I am currently working on a design which requires me to design a module that combines 2 input streams of data & output it into a single output stream. To elaborate more, i can describe it with an example :
So basically the output preserves the order of the inputs (input0 of the same clk followed by input1 & then move to the ip0 of the next clk). I know we need to stall the input stream at some point because the output rate is getting halved.
My idea so far: I was thinking of having the arbiter after the FIFO (so basically store the 2 input dwords into the FIFO, then keep popping the FIFO, store the rddata with dword0 & dword1 in a temp register & in a state-machine assign the dword 0 to output first & then in the next state assign the dword 1 to output. At this point assert the read en / pop the FIFO.
So, do you guys have any suggestions to improve the performance or do you see any issues with the plan so far ?
CLK | Input Data Word 0 | Input Data Word 1 | Output |
0 | a | b | - |
1 | c | d | a |
2 | e | f | b |
3 | g | h | c |
--- | --- More data --- | -- More data --- | d |
So basically the output preserves the order of the inputs (input0 of the same clk followed by input1 & then move to the ip0 of the next clk). I know we need to stall the input stream at some point because the output rate is getting halved.
My idea so far: I was thinking of having the arbiter after the FIFO (so basically store the 2 input dwords into the FIFO, then keep popping the FIFO, store the rddata with dword0 & dword1 in a temp register & in a state-machine assign the dword 0 to output first & then in the next state assign the dword 1 to output. At this point assert the read en / pop the FIFO.
So, do you guys have any suggestions to improve the performance or do you see any issues with the plan so far ?