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Suggestions for my fifo arbitration / path merge design

rahdirs

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I am currently working on a design which requires me to design a module that combines 2 input streams of data & output it into a single output stream. To elaborate more, i can describe it with an example :
CLK​
Input Data Word 0​
Input Data Word 1​
Output​
0​
a​
b​
-​
1​
c​
d​
a​
2​
e​
f​
b​
3​
g​
h​
c​
---​
--- More data ---​
-- More data ---​
d​

So basically the output preserves the order of the inputs (input0 of the same clk followed by input1 & then move to the ip0 of the next clk). I know we need to stall the input stream at some point because the output rate is getting halved.
My idea so far: I was thinking of having the arbiter after the FIFO (so basically store the 2 input dwords into the FIFO, then keep popping the FIFO, store the rddata with dword0 & dword1 in a temp register & in a state-machine assign the dword 0 to output first & then in the next state assign the dword 1 to output. At this point assert the read en / pop the FIFO.
So, do you guys have any suggestions to improve the performance or do you see any issues with the plan so far ?
 

ads-ee

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Your idea only works if the two input streams have identical write timing (assuming your design uses a single FIFO of dword0 & dword1 width).

If the input streams aren't arriving with identical timing then you should use two separate FIFOs one for each dword0 and dword1 input streams. Either datapath can be stalled independent of the other and the merging of the output doesn't have to be interleaved (unless that is part of the requirements).
 

    rahdirs

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rahdirs

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Your idea only works if the two input streams have identical write timing (assuming your design uses a single FIFO of dword0 & dword1 width).

If the input streams aren't arriving with identical timing then you should use two separate FIFOs one for each dword0 and dword1 input streams. Either datapath can be stalled independent of the other and the merging of the output doesn't have to be interleaved (unless that is part of the requirements).
Yes, the plan for the current design is to have the writes from both the input streams at the same time. If not, then it would be difficult to maintain the ordering of the inputs at the output stream when both the input streams have different write timings.

--- Edited to answer the part about interleaving ----
Yes, 1 of the the requirement is that the outputs maintain the order between the input data stream (example below).
So, the output needs to be :
op clk 1 -> ip0, clk0
op clk 2 -> ip1, clk0
op clk 3 -> ip0, clk1
op clk 4 -> ip1, clk1
... etc
 
Last edited:

vGoodtimes

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the op's first suggestion seems fine. in terms of implementation, you might be able to get other implementations of a width-changing fifo, or just use a core for this.

but this assumes that both inputs always both have valid data or both don't have valid data on each cycle. eg, never a case where one stream has valid data and the other doesn't.
 

KlausST

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Hi,

Either both input data need to be in sync to a common "valid" signal (clock signal)
Or you need two independent "valid" signals, one for each input.

Then it depends how fast the input data rate is compated to your system clock.

If possible, I'd use one common FIFO.

Klaus
 

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