Suggestions for low cost ASIC synthesis tool

[n1cm0c]

I'm doing full custom analog blocks which need some simple FSM digital blocks.
Our digital people are too busy using Synopsys/Cadence/Mentor latest generation tools to design huge digital ASICs in nanometer technologies, so there's no-one to help me write VHDL/Verilog synthetisable code and use these tools to generate a SPICE/Spectre/Hspice netlist that I can use to simulate my full circuit (98% analog, 2% digital).

I know I could use VHDL-AMS or Verilog-AMS to model everything together, but I think this is overkill, since the digital part is so small. My simulations will take longer, I'll need more expensive licenses, and probably also learn a "new" language (the -AMS).

In the final phase of my design the digital part will be synthetised by the digital experts, and then I'll get back the full SPICE netlist with all parasitics, etc.

But before I get there I'd like to be able to synthetise my FSMs, using some simple, low-cost and easy to use tool, so that I could have SPICE netlists of the digital part I could use in my simulations. I have a library of digital standard cells with full layout, and SPICE netlists for them, and I'd like to synthetise logic using that library.

I am looking for something similar to the berkeley tools (octtools, msii, mvsis, sis, whatever), but commercial (with some support), and able to take RTL VHDL as input. Maybe something like Exemplar Logic? Many years ago I recall using something like that, I think.

So, my question to you digital experts is: Could you suggest an ASIC logic synthesis tool that accepts RTL VHDL and outputs a gate level netlist (against a standard cell library), preferably in SPICE/HSPICE/SPECTRE syntax ?

Thanks for any help!

 

[semiconductorman]

any synthesis tool will do exactly that , that is take RTL and convert it to gate level net list . But they are in simple verilog format. I don't know how large your design is , you did say it was 98% ananlog but the question is how big is digital not in % but gate count / area . If your fsm is not too big you could hand-design it . I know that art is not followed anymore most of us digital desingers are limping only on eda tools but then again I see no reason why you should n't handcode.

 

[n1cm0c]

Thanks for your suggestion. I had to do other stuff, and I also checked all softwares I could find. it looks like that only the Alliance tool set is free and could do what I want, simple synthesis of FSMs for control of features, test sequences, etc, of my 98% analog design.

The FPGA synthesis tools could be a low-cost option, but then none seems to allow me to map to a different technology table, or at least to obtain a gate-level verilog netlist from an RTL VHDL or Verilog input.

SIS could also do it, or MV-SIS, but these are very old tools and I don't want to spend time learning how to write files for it. The whole point of writing the FSMs in VHDL or Verilog is to make it more clear and maintainable, instead of schematics built from K-maps or whatever else the designer did by hand.

As far as I could find out, there are no low-cost ASIC synthesis tools that take RTL VHDL or Verilog input and generate gate-level netlists against a standard cell technology library.

 

[Arturi]

Hi,

What if you write your VHDL code, then use a low cost FPGA synthesizer to generate the netlist, and then write a perl script to map the standard gates to your spice netlist. You can set a dont_use_list so that you only use a reduced number of cells that you could parse and translate to transistors.

Wouldn't that work?

cheers

 

[Manjunatha_hv]

Hello,


Why can't you try to use Incentia, Design Craft for your ASIC synthesis...
This is a low cost option (as compared to Synopsys or Cadence synthesis tool)...
I think this serves your purpose....

**broken link removed**



--manju--

 

[boardlanguage]

If your company already has Design Compiler or some other ASIC-synthesis tool, then just go through one of the tutorial exercises. They give you an overview of the synthesis process, and after finishing it, you'll be able to synthesize the small piece of your design.

Once you have the gate-netlist, you should be able to use one of the other tools to extract a layout/transistor-netlist from the gate-netlist.

I don't see any reason to 'buy a lowcost synthesis tool.' If your company already has one of the big synthesis tools (DC, RTL Compiler, etc.), there is no reason to buy a secondary tool that will only be used for 1 small tiny circuit.

 

[Arturi]

Once you have the gate-netlist, you should be able to use one of the other tools to extract a layout/transistor-netlist from the gate-netlist.

Just for my info (I am a front-end engineer): Which tool extracts a layout transistor netlist from the gate-netlist?

cheers!

 

[n1cm0c]

Thanks for all the replies!

I'll look into the possibility of using a FPGA synthesizer and force only mappings to basic logic gates, since I think I have a script that translates a Verilog gate level to spice.

I'd like to hear more about that, if somebody could give advice.

Incentia is nice, but I can't have one more tool purchased... At least not a tool that needs support, training, etc. FPGA synthesis tools are available in-house, and I have access to them.

The big-iron synthesis are available, but not to my side of the company... No licenses for my machine!
i am on the analog aisle, and currently I have to wait until a digital person can be assigned for 15 seconds to my project to re-synthetise FSMs, whatever.

My solution has been to do it by hand, write spice netlists using cells from the library, and finsih my design this way. Later everything is re-done by the digital man in VHDL/Verilog (I don't know, I don't see it) just before the final check prior to tapeout.

Thanks again for all the advice!