srivatsan said:I dont know how many of you have actually fabricated a chip. I would be fabricating my analog devices by 0.5um technology, check www.mosis.org, AMC 0.5 runs. I would like to have some inputs regarding the precautions and necessary 'circuits' when fabricating. I am fabricating op-amps and few discrete devices and finally ADC in one chip. Let me know the possible problems that can be encountered. :?: :roll: thank you in advance........
DoctorX said:Watch out for layer mapping, you do not want MOSIS to miss out a few layers on you, say M1 or Poly.
Those are exactly what I wanted to say.DoctorX said:Watch out for extraction rules, you do not want to miss some parasitic PN diodes, which can wreck havoc, or do inaccurate capacitance extractions.
I'm more than willing to see that. Thanks!DoctorX said:I modified those rule files are willing to share. Just ask.
wide metal rule: metals fatter than xxx um must have double spacing. TSMC said 10 um, MOSIS said 1 um. I use 2 um.
srivatsan said:i have one more question: since my circuit would be drawing good amount of current, inorder to prevent the electromigration and other associated problems when a thin wire is carrying little heavy current, I need to have the width of the wire wider. how am i suppose to calculate the width for a given current? if you have done this befor let me know. thanks.
There is another thing that can send RF designs (and your fabbed chips) directly to TrashCo (C) or WasteManagement (C) depending on which one you contract: 3-side or 4-side extraction for Source/Drain diffusion capacitance perimeter, i.e., the Cjsw stuff. This difference is very, very bad for shared drain transistors and for RF designs, where parasitic caps are ruling Queens.
I know it 'cause it happened to me. Most books do not care to talk about it in detail, maybe the writers did not have hand-ons; and most RF engineers say that they do not know, either considering them as "trade secrets" or admitting it will bring back memories of bad experiences. Anyway, pay attention to it. If this is too vague, ask please.
Japp said:There is another thing that can send RF designs (and your fabbed chips) directly to TrashCo (C) or WasteManagement (C) depending on which one you contract: 3-side or 4-side extraction for Source/Drain diffusion capacitance perimeter, i.e., the Cjsw stuff. This difference is very, very bad for shared drain transistors and for RF designs, where parasitic caps are ruling Queens.
I know it 'cause it happened to me. Most books do not care to talk about it in detail, maybe the writers did not have hand-ons; and most RF engineers say that they do not know, either considering them as "trade secrets" or admitting it will bring back memories of bad experiences. Anyway, pay attention to it. If this is too vague, ask please.
What do you mean ?, are the pex-tools extracting to few/many parasitics or is it the circuit models you are talking about ?
Please tell more details...
srivatsan said:i need to know about the ESD protection that is provided by the MOSIS people. also i see that they fabricate with clean environment but what about ESD circuits inside the chip? do they add it like default or is it upto me to get a circuit for that?
anyone who has fabricated .. plz answer.. thanks in advance..
srivatsan
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