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Sudden decrease in SNR of pipeline ADC

Chinmaye

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Dear all,
I am trying to calculate the SNHR of the pipelined ADC in Cadence. Its a 12-bit ADC with sampling rate 40 MSPS. I tried to calculate the SNHR of the input signal close to 9MHz and i got an SNHR of about 70dB. But when I increase the frequency of the input signal to around 11MHz, the SNHR drops by almost 20 dB. I am unable to understand this behavior. Could someone please explain as to why this can be happening?

Thanks,
Chinmaye
 

sutapanaki

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Where is your input signal coming from? How do you set up the calculation in cadence?
 

Chinmaye

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Where is your input signal coming from? How do you set up the calculation in cadence?
The input signal is a sine wave from Analog library and I use spectral measurement in cadence to measure SNHR. I have considered around 30 cycles for measurement.
 

sutapanaki

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So, you are saying you measure the SNR of an ideal voltage source and it varies by 20dB?
 

dick_freebird

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If there is a sample/hold stage at the input then
its settling-time behavior may have effects beyond
what forward-path small signal analysis might
indicate. The sampling and hold mode transitions
are time-domain large signal. The settling tails
might be significant at at 10MHz / 100nS, a problem
at 90nS and no prob at 111nS input period, like.

I don't do and have never done such calculations
but it would seem to me that if you put the two
cases up against each other (maybe in Excel
where you can break down the equation to its
feature-specific elements) the discrepancy
based on input signal frequency ought to reveal
itself, and lead you to "why?".
 

KlausST

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Hi,

If you use FFT, then maybe it's due to window size mismatch..

Klaus
 

Chinmaye

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Thank you for the reply. I figured out it is due to SHA.
 

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