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Substrate injection noise in DC DC converter

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alokmittal05

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Hello,

I need help to conceptually understand the phenomenon of substrate noise injection in DC- DC converter?
Internal circuit sharing epi with high switching epi inject current into parasitic but, that must be avoided.
Can anyone help me to understand this better?
 

dick_freebird

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Every source and drain and well is part of a PN
junction capacitor.

When they move, voltage-wise, displacement
currents flow in / out of the capacitors. One end
of N+ S/D and NWell / deep NWell is the Pepi in
most modern CMOS processes. So you will pump
charge into / out of the epi locally and it will
distribute itself according to resistivity and
drift / diffusion. Until it gets back to equilibrium
there will be body effect impact on device
thresholds / matching, pickup of current from
"outside the circuit" (i.e. the bits you neglect for
convenience, like the substrate mesh), and
noise from the discrete and random collection
of those carriers across any nearby (relative
to diffusion length) junctions. High impedance
nodes nearby a large hard-switching device
("aggressor") are the likeliest "victims".

If you care at all about "noise" in any of these
forms then you need to impose your will on
where it goes, and how.

That is where guardrings and substrate taps,
and their qualities of routing to which supply
rail, come in.
 

alokmittal05

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Thank you for your reply.
altough I understand bits and pieces of what you are saying I need to read more about this topic for better clarity. sadly I couldn't find much on the web. can you point me to any good reference?
 

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