Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

substrat contact in std cell

Status
Not open for further replies.

amitabh262002

Member level 2
Joined
Jul 24, 2007
Messages
49
Helped
8
Reputation
16
Reaction score
6
Trophy points
1,288
Activity points
1,661
Hi
i am delevloping std cell library.
can any one tell me how to give substrat connection to any Gate like AND...

---------------------------------------------VDD
PMOS
NMOS
-------------------------------------------------VSS
this is my rough representation of a cell,pls tell me where shoud i give substrat connections.
 

You can try putting them right under the VDD and VSS supply rails. That ways, you can save a lot of space!!!

--cmos_dude
 

p substrate can be given below the VDD rail while the n-substrate can be placed below the VSS rail, this is the most preferred way.
This saves a area also.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top