substraction in vhdl

[jojo26]

hey i'm a newbie ,i want to have a simple substraction between two std logic vectors so i converted them into signed,but when i tested this code it didn't work correctly for example 8 +(-5) gave me (-1021) istead of 3 !!!

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sub is 

port (  
    clk         : in    std_logic;
    rst         : in    std_logic;  
    a,b    : in    std_logic_vector (10 downto 0);
    c   : out  std_logic_vector (11 downto 0)  
);
end sub;

architecture beh of sub is
signal p1,p2,p3 :signed (11 downto 0);

begin
  p1 <= signed ('0'& a) ;
  p2 <= signed ('0'& b) ;
    process (clk, rst)
        begin
            if (rst = '1') then
                p3 <= "000000000000";
            elsif (clk'event and clk='1') then  
          
                
                    p3 <= p1 + p2;

            end if;             
    end process;
    c<= std_logic_vector(p3);
end beh;

the compilation is working.
thanks a lot
regards
jojo26