Submodule size in hierarchical flow?

[wizard]

I am doing a 3.6 million instance design.

Do you think it's efficient to run a flat flow?

I'm planning for a hierarchial flow. What's the submodule size do you recommend? How large module can a commodity tool(ICC, SOCE, magma) handle? EDA tool vendors are good at hyping. I'd like to hear some suggestion from engineers.

Thanks.

 

[rohanhelio]

No. of instances of design, is just a single parameter to represent the complexity of the design.
Please provide other details like the area, frequency, power domains & methodologies, etc. you are suppose to use.

Anyway, as per my knowledge all these three tools (ICC, SOCE & Magma) have the capability to handle a design of 3.6 million instances.

It mainly depends, with which tool you are comfortable.

Generally in big vlsi companies, they have there own flow with several scripts & wrappers to harness the tool's capability as per their need.

For an example:
I just completed a fullchip project of 45nm technology, having about 20 million gate count. And we used Magma for floorplanning, powerplanning, routing. For backend checks, we used Hercules, Celtic, PTSI with few more internal tools.
And it was really a very big design with almost all low power methodologies.

All i want to say may be as per the requirement you have to use other tools in conjunction with any of those three.

Hopes this information will be helpful for you.

 

[wizard]

I agree with you. But my point here is mainly about efficiency. I agree these tools can handle this. But if it takes a week to finish placement flatly, it don't make sense do it in a flat way.

How long did it take for your design in a flat way if you'd tried it?

No. of instances of design, is just a single parameter to represent the complexity of the design.
Please provide other details like the area, frequency, power domains & methodologies, etc. you are suppose to use.

Anyway, as per my knowledge all these three tools (ICC, SOCE & Magma) have the capability to handle a design of 3.6 million instances.

It mainly depends, with which tool you are comfortable.

Generally in big vlsi companies, they have there own flow with several scripts & wrappers to harness the tool's capability as per their need.

For an example:
I just completed a fullchip project of 45nm technology, having about 20 million gate count. And we used Magma for floorplanning, powerplanning, routing. For backend checks, we used Hercules, Celtic, PTSI with few more internal tools.
And it was really a very big design with almost all low power methodologies.

All i want to say may be as per the requirement you have to use other tools in conjunction with any of those three.

Hopes this information will be helpful for you.

 

[rohanhelio]

Mainly it depends upon the complexity of your design.
But, ok..........have a look of these links (please read carefully):

https://www.deepchip.com/items/snug07-08.html
https://www.deepchip.com/items/0479-07.html

I hope, you'll get all your answers.

Rohan

 

[rohanhelio]

What happened wizard?
Have you got your answer?

 

[samirkag]

Sure. Break her up. 3.6Mn PIs would hurt TAT and QoR.

 

[shelby]

Another interesting article on Magma tools with some run-times quoted ...

https://www.deepchip.com/items/0479-06.html