Sub-threshold SRAM Design

[loves86137]

Be a postgraduate student, I study on the design of sub-threshold SRAM now. The papers I have been collecting are all emphasize how to increase the stable of SRAM Cell. Such as write noise margin、read noise margin and so on. However, there are no references show how these periphery circuits (ex. column decoder, read buffer……and so on.) are designed in the sub-threshold region.

I know CMOS logic circuit works in the sub-threshold region will lead to much longer time to rise or fall, and this delay might cause SRAM work failure. Above problem has been tormenting me for weeks, therefore I hope to get helps. Are there anyone who masters or works in this field could give me some advices or information? Thank you!!

 

[erikl]

Do you know the book Sub-threshold Design for Ultra-Low Power Systems by Alice Wang et. al. ?
© Springer 2006

It offers a very good overview (also) on sub-threshold memories (Chap. 7), especially on sub-threshold SRAM (7.2, p. 115).

Sub-chapter Enabling Sub-threshold Read (p. 133) describes appropriate read buffers.

 

[loves86137]

Do you know the book Sub-threshold Design for Ultra-Low Power Systems by Alice Wang et. al. ?
© Springer 2006

It offers a very good overview (also) on sub-threshold memories (Chap. 7), especially on sub-threshold SRAM (7.2, p. 115).

Sub-chapter Enabling Sub-threshold Read (p. 133) describes appropriate read buffers.

erikl, thanks for your reply! Does this book describe other periphery circuits(ex. column decoder, write buffer……and so on.)? Thank you!

 

[erikl]

Does this book describe other periphery circuits(ex. column decoder, write buffer……and so on.)? Thank you!

Yes, but not in great detail. They show an overview over their 256kb 65nm SRAM testchip with its architecture diagram. See p. 140 via the above mentioned link. Pages 138..140 can be looked at.

All of the peripherals use static CMOS logic for simplicity and for functional robustness in sub-threshold.

 

[loves86137]

Yes, but not in great detail. They show an overview over their 256kb 65nm SRAM testchip with its architecture diagram. See p. 140 via the above mentioned link. Pages 138..140 can be looked at.

erikl, thank you very much! I am going to try to read this book. If I have any question, would you please give me some advice again? Thank you very much!