[SOLVED] stuck at faults implementation using FPGA

[guru2kiot]

Hello,
Can anyone suggest me how to implement stuck-at-faults (stuck-at-0 or stuck-at-1 faults) using FPGA. In my coding i have used stuck at faults using force the signals. Its able to done successfully in simulation level..but implementation its not able to synthesis using FPGA..so can anyone suggest me how to implement stuck-at-faults using FPGA??

 

[dpaul]

This one would help you: https://embdev.net/topic/235605

 

[guru2kiot]

Hello dpaul,
Thank you very much for your valuable response......above given link is surely very useful one for stuck at faults. In that discussion faults injections signals and its syntax followed by vhdl method. same like that is it possible to inject the faults in verilog ???

 

[dpaul]

I have never implemented fault modeling, just know it in theory.
I have just glanced through the link and posted it here.
Replace the VHDL syntax by Verilog and play around with the suggested methods.

Search using phrase : stuck at fault + Verilog


https://groups.google.com/forum/#!topic/comp.lang.verilog/G83H0o7GW1Y

There should be more, just filter out as per your requirements.