Can anyboby explain how to detect stuck at faults in case of a square pulse in verilog?
I would like to modify the qn as to detect the loss of a pulse
The situation is like, i have an input square pulse and have to detect the situations when it is lost and become low always or may become high always.
If the square pulse is a clock-like signal then use a faster clock and synchronize and edge detect the synchronized version, then have a timeout counter that resets each time an edge occurs. If the timeout counter saturates (i.e. all 1's) then the counter stops at the saturation count and the stuck detection goes active.
The simplest solution to a missing pulse detector is a one shot that is retriggerable from the pulse itself set to the time interval expected or better, the pulse synchronized by a PLL clock which the missing pulse over +/-1/2 of the clock interval, with detection also on extra pulses a consideration.
You don't want to use a 555 and wish to use modelsim to simulate the function.instead of using 555 can i develop it by any other means because i need modelsim simulation for that
I suggested a method to perform the action without a 555 and you ask for a different suggestion?Thank you so much. I came across this. Can you suggest me any other
You're statements in post #8 seem to contradict each other:
You don't want to use a 555 and wish to use modelsim to simulate the function.
I suggested a method to perform the action without a 555 and you ask for a different suggestion?
So what do you want? You seem to already know what you want, so describe exactly what you want, instead of some vague question (post #1) with no requirements or test cases to verify functionality.
The method I mentioned can be easily written in VHDL/Verilog and simulated in Modelsim. I've used circuits like this many times. I'm actually using one in some common library debounce code I wrote a number of years ago.
Thank you for suggesting that method, can you suggest any other
Like what? You obviously are looking for something specific, so explain why the simplest solution is inadequate for what you are doing.
i saw this method already in a paper so i wanted to replace it with any other better method (in terms of lesser area or power when synthesized), so that i can compare these two
Thank you so much. I came across this. Can you suggest me any other
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instead of using 555 can i develop it by any other means because i need modelsim simulation for that
in terms of lesser area or power when synthesized
i need modelsim simulation
None of which will suffice in meeting the criteria set forth after a dozen posts, which are: "better" synthesis and modelsim simulation (i.e. VHDL/Verilog).I can think of a dozen ways to make a 1 shot and have never used a 555 in 40yrs.
How about a DM74123N vintage CMOS 1 shot, with a pot set to 1% or a logic state machine... Or ....