Stuck at fault detection of a square pulse

[tv123]

Can anyboby explain how to detect stuck at faults in case of a square pulse in verilog?

 

[harpv]

Can anyboby explain how to detect stuck at faults in case of a square pulse in verilog?

What do you mean by fault in square pulse ?

Stuck at faults are detected in a physical circuit and not in a waveform. Do you mean to ask, how to detect stuck at faults in a pulse generator circuit ?

 

[tv123]

I would like to modify the qn as to detect the loss of a pulse

 

[harpv]

I would like to modify the qn as to detect the loss of a pulse

So you need a pulse detection circuit? Please look at this thread, maybe this is what you are looking for.

A simple google search could have easily popped this up.

 

[tv123]

The situation is like, i have an input square pulse and have to detect the situations when it is lost and become low always or may become high always.

 

[ads-ee]

The situation is like, i have an input square pulse and have to detect the situations when it is lost and become low always or may become high always.

If the square pulse is a clock-like signal then use a faster clock and synchronize and edge detect the synchronized version, then have a timeout counter that resets each time an edge occurs. If the timeout counter saturates (i.e. all 1's) then the counter stops at the saturation count and the stuck detection goes active.

 

[D.A.(Tony)Stewart]

The simplest solution to a missing pulse detector is a one shot that is retriggerable from the pulse itself set to the time interval expected or better, the pulse synchronized by a PLL clock which the missing pulse over +/-1/2 of the clock interval, with detection also on extra pulses a consideration.

 

[tv123]

If the square pulse is a clock-like signal then use a faster clock and synchronize and edge detect the synchronized version, then have a timeout counter that resets each time an edge occurs. If the timeout counter saturates (i.e. all 1's) then the counter stops at the saturation count and the stuck detection goes active.

Thank you so much. I came across this. Can you suggest me any other

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The simplest solution to a missing pulse detector is a one shot that is retriggerable from the pulse itself set to the time interval expected or better, the pulse synchronized by a PLL clock which the missing pulse over +/-1/2 of the clock interval, with detection also on extra pulses a consideration.

instead of using 555 can i develop it by any other means because i need modelsim simulation for that

 

[ads-ee]

You're statements in post #8 seem to contradict each other:

instead of using 555 can i develop it by any other means because i need modelsim simulation for that

You don't want to use a 555 and wish to use modelsim to simulate the function.

Thank you so much. I came across this. Can you suggest me any other

I suggested a method to perform the action without a 555 and you ask for a different suggestion?

So what do you want? You seem to already know what you want, so describe exactly what you want, instead of some vague question (post #1) with no requirements or test cases to verify functionality.

 

[tv123]

You're statements in post #8 seem to contradict each other:

You don't want to use a 555 and wish to use modelsim to simulate the function.


I suggested a method to perform the action without a 555 and you ask for a different suggestion?

So what do you want? You seem to already know what you want, so describe exactly what you want, instead of some vague question (post #1) with no requirements or test cases to verify functionality.

Hi ads-ee, i got mixed up with the replies. i meant that i came across the approach that you described and i wanted to know whether there is any other method.
555 reply was for sunnyskyguy

 

[ads-ee]

The method I mentioned can be easily written in VHDL/Verilog and simulated in Modelsim. I've used circuits like this many times. I'm actually using one in some common library debounce code I wrote a number of years ago.

 

[tv123]

The method I mentioned can be easily written in VHDL/Verilog and simulated in Modelsim. I've used circuits like this many times. I'm actually using one in some common library debounce code I wrote a number of years ago.

Thank you for suggesting that method, can you suggest any other

 

[ads-ee]

Thank you for suggesting that method, can you suggest any other

Like what? You obviously are looking for something specific, so explain why the simplest solution is inadequate for what you are doing.

 

[tv123]

Like what? You obviously are looking for something specific, so explain why the simplest solution is inadequate for what you are doing.

i saw this method already in a paper so i wanted to replace it with any other better method (in terms of lesser area or power when synthesized), so that i can compare these two

 

[ads-ee]

i saw this method already in a paper so i wanted to replace it with any other better method (in terms of lesser area or power when synthesized), so that i can compare these two

Sounds like an academic research project...

I don't know of a better way to do it. I always prefer something that is easy to understand and is bug free than going with something convoluted/tricky/clever just for the sake of 1 nA power savings ;-)

If you can't use a counter then there isn't any other reliable way to determine if a given amount of time has passed with no pulse. Everything else ends up being "analog" or using digital delays in an analogish way (e.g. delay lines with LUTs).

Besides if you are doing research, then you should probably be coming up with a new method on your own (as opposed to asking someone to give you a new method). After coming up with that new method you'll have to prove it works better to convince people like me that produce fielded products.

 

[D.A.(Tony)Stewart]

Thank you so much. I came across this. Can you suggest me any other

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instead of using 555 can i develop it by any other means because i need modelsim simulation for that

I can think of a dozen ways to make a 1 shot and have never used a 555 in 40yrs.
How about a DM74123N vintage CMOS 1 shot, with a pot set to 1% or a logic state machine... Or ....
pick one
https://www.digikey.com/product-sea...1&stock=1&quantity=0&ptm=0&fid=0&pageSize=500

 

[ads-ee]

in terms of lesser area or power when synthesized

i need modelsim simulation

I can think of a dozen ways to make a 1 shot and have never used a 555 in 40yrs.
How about a DM74123N vintage CMOS 1 shot, with a pot set to 1% or a logic state machine... Or ....

None of which will suffice in meeting the criteria set forth after a dozen posts, which are: "better" synthesis and modelsim simulation (i.e. VHDL/Verilog).

This is a good example of how a vague questions that doesn't give details of what the OP is actually looking to accomplish can run for many posts before something of substance actually comes out and also results in answers like SunnySkyguy's latest that don't match the requirements because it so darn hard to find those requirements in so many separate posts!

 

[D.A.(Tony)Stewart]

Yes original problem is vague with symptom only.

Try to give broader scope in future on post #1
Is it a metastable or missing pulse from a race condition?
Then re-sync critical path signal to master clock using FF to avoid race and missing pulse rather try to detect the fault with a shot shot.

 

[tv123]

I am really sorry for creating such a big confusion. I want to design a circuit to detect the attached waveform. I tried using two simultaneous counters and it is working fine. I wanted to know whether there is any other design so that i can do it in verilog hdl