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Struggling with Pad design error for IC design....CBVIA1.R.1.OUTER.P60 ratio of outer VIA1 to CB >= 0.05

jack63

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Dear All,
I'm new to this board. My user name has generated controversy in the past, but I will do my best to stay keep it to Analog IC design and layout which is what I do to make a living.
I'm struggling with the layout rules of a pad in TSMC 180nm. I am getting the error CBVIA1.R.1.OUTER.P60 when trying wire bond layout rules. I don't have clue how to fix this problem. If anybody has experience with this please help. I'm giving this EDA board a try as some of the info here is valuable. Thanks in advance! Please let me know if you need further information.
Sincerely,
Jack
 

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