Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Strong PLL Jitter on AMCC405EP CPU

Status
Not open for further replies.

mr_ghz

Full Member level 5
Joined
Apr 1, 2002
Messages
289
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,298
Activity points
3,551
Hi all

I designed a CPU board with an AMCC 405EP controller. The whole board works well with a Linux and QT.

By EMC testing we saw a strange behaviour of the board: The 266MHz CPU clock has a strong jitter on it, but the 66MHz input clock has not.

Let me explain the design a little bit more: The CPU SYSClk is driven by a 66MHz crystaloscillator. Pegel, jitter everything OK. The PLL inside the CPU runs on a VCO frequency of 800MHz (66MHz*12). The forward divider is set to :3 this gives the corefrequency of 266MHz. On all frequencies which are created from this coreclock (MemClk, PLBClk, ...) I measure the jitter. The jitter looks like an instabile loopfilter of the PLL.

PLL has a separete VCC as mentioned in the datasheet, also supply noise is low.

The PLL has some 'tunebits' which are not clearly described in the datasheet. When I use the given values --> jitter occurs. The I played a little bit with the tuningbits. I found several combinations which runs fine (also by cooling / heating the board, over- and undervoltage).

Do anyone know this behaviour of this CPU?
Do anyone know the exact meaning of these tuningbits?
Some more ideas?

Thanks in advance
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top