roudra
Newbie level 1
hello all...
i have a doubt on the ddr3 strobe signal. I am doing SI on my board and i see the following stuff related to DDR3 read and write transactions.
1. the write preamble is a short half CLOCK PERIOD negative pulse on DQS strobe while read preamble is a full clock negative pulse.
2. the write data is shifted 90 degree w.r.t strobe while read data aligns itself with the strobe.
now all of these follows JEDEC spec for DDR3.
now i got a couple of Tektronix document online that says that for write DDR3 operation the strobe signal should have a positive transition. is there any information i am missing?
thanks
Roudra
i have a doubt on the ddr3 strobe signal. I am doing SI on my board and i see the following stuff related to DDR3 read and write transactions.
1. the write preamble is a short half CLOCK PERIOD negative pulse on DQS strobe while read preamble is a full clock negative pulse.
2. the write data is shifted 90 degree w.r.t strobe while read data aligns itself with the strobe.
now all of these follows JEDEC spec for DDR3.
now i got a couple of Tektronix document online that says that for write DDR3 operation the strobe signal should have a positive transition. is there any information i am missing?
thanks
Roudra