Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Strobe signal DDR3 Preemble

Status
Not open for further replies.

roudra

Newbie level 1
Joined
Jan 30, 2008
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,288
hello all...

i have a doubt on the ddr3 strobe signal. I am doing SI on my board and i see the following stuff related to DDR3 read and write transactions.

1. the write preamble is a short half CLOCK PERIOD negative pulse on DQS strobe while read preamble is a full clock negative pulse.
2. the write data is shifted 90 degree w.r.t strobe while read data aligns itself with the strobe.

now all of these follows JEDEC spec for DDR3.

now i got a couple of Tektronix document online that says that for write DDR3 operation the strobe signal should have a positive transition. is there any information i am missing?


thanks
Roudra
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top