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String to std_logic_vector in VHDL

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raghava

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HI all,

Can anybody tell how to convert from string to std_logic_vector in VHDL.
I am newbie to VHDL.

Any help is appreciated.

Regards
 

I got this code from **broken link removed**.
Enjoy!

-- converts a string into std_logic_vector

function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;


--
Amr Ali
www.embedded-tips.blogspot.com
 

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