Hi,
Specify the timing. Is it picoseconds or hours?
What supply voltage and what logic family?
Klaus
The problem with the circuit you propose (monostable and NAND gate) is the NAND gate. You want a '0' output if EITHER the monostable is low (in the case of the pulse being shorter than the monostable period) OR the pulse is low (in the case of the pulse being longer than the monostable period).
Therefore the output should be '1' only when BOTH the input line and the monostable are high - so you want an AND gate.
(This assumes that the \Q\ output of the monostable is being used - that's the one that is normally high and low when the monostable is triggered.)
Drawing out the timing diagram of the situation when the pulse is longer than the monostable period and putting that with the one you drew in the first post would show you the solution.
Susan
Did you read post#4?ok is there any possible way to stretch it for around 100ns digitally without using the RC?
implementing a counter would be complicated especially that i need to delay it for only 2 clock cycles and i guess the counter would stretch both pulses?100ms is a lot for an IC. If you have a clock, use a counter for the timing.
Why particularly?implementing a counter would be complicated especially that i need to delay it for only 2 clock cycles and i guess the counter would stretch both pulses?
I'm not sure what we are currently talking about because the original 100 ms delay shrunk to 100 ns in the meantime. There's a certain state of the art for reset generators, usual delays are in a several 10 to several 100 ms range. They are implemented as digital timers with e.g. high kHz oscillator to save chip area. Purely analog implementations with pF capacitor and pA current source would be possible nevertheless, probably less accurate.
Why particularly?
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An analog reset timer with external timing capacitor https://www.ti.com/lit/gpn/tps3895
I'm trying to do both variants, so i thought delaying it digitally would be easier.Hi,
In post#3 you talk about 50...100ms.
Now you talk about 40ns.
Why?
This is more than a million factor away...
Klaus
Conceptually, how about you trigger the counter with the rising edge of your short pulse and let it count for as long as you need. When it is done counting, it generates a transition, say low to high, kind of ready signal. Then use a sort of a RS latch which is asserted low with the falling edge of your short pulse and deasserted to high with the counter ready signal.
Hello, i have a digital output with varying pulse sizes and i want to stretch the 0 output for a constant T+ 0 pulse time. I have tried using a monostable multivibrator with a NAND gate but the problem i got is that the length of the pulse remains constant, which could be a problem if the pulse width is greater than the multivibrator output so how to add this time constant to the original pulse width instead?
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View attachment 153710
here's an image of the desired output
Yes, of course you can achieve it. Make the flow diagram of the thing and based on it design the circuit.
Here is a dirtier way of perhaps doing it. I did not simulate the circuit, so there is some possibility of error, but I hope you'll get the idea. I have assumed your short pulse is in sync with the clock as you show in your diagrams.
View attachment 153900
Trigger from the negative edge, and hold till positive edge. Retrigger again at positive edge.
Thats the logic. Just have to implement it.
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Childish problem. Whats the big concern ?
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