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stratix Enhanced /Fast PLL, Gclk, Rclk question

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hayang

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hi, I am new to stratix FPGA design, maybe my question is too simple.
what is the relation between Enhanced/Fast PLL and Global/Regional clock?
our current design uses a lot of clocks, and the Global clock number are not enough, so we need to use Regional clocks, but the pin locations have been fixed by the PCB board, what happens if the following condition happens: one Regional clock is for a certain region, and all the design logic is also constrained in this region, but there is some pin connnecting to those logic that is outside this region, is this a problem?
can any experienced FPGA designer give me a hand?
thanks a lot
harry
 

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