Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

strange strcuture of EEPROM cell

Status
Not open for further replies.

afujian

Member level 4
Member level 4
Joined
Mar 26, 2010
Messages
70
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Location
china
Visit site
Activity points
1,715
Hi,Can anyone explain why there is a port PB connnect to the float gate through a MOS capacitor as shown in the EEPROM cell?
EEPROM.JPG
 

I'm guessing this represents some parasitics, is all.
Where those parasitics bleed / return charge to, is
going to affect read times and so on. It looks like a
pretty trivially-sized device and is only representing
some capacitance.

Sometimes you put those ports in for design purposes
(observability in simulation) and it's not worth the
time to take them back out just to not confuse others.
 

hi dick_freebird ,thanks for your reply,I'm afraid this does not represent the parasitic cap,because the data line from the control logic is connected to the port PB,so,this port may have some relationship with programming, is that possible?
 

Do you have the layout of this cell or program condition?
I guess that programming might be via pch5.
 

I think it could be a PRESET input. By applying a voltage step to VDD resp. to GND to this input, one can inject or remove a certain amount of charge to/from the gate, so generating a required preset condition.
 

sorry ,there's only schematic

- - - Updated - - -

hi erikl ,the voltage of port PB has three values ,0 5V 15V respectively
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top