redpixel
Newbie level 4
Hi all!
I was trying to simulate phase noise getting divided down by a DivideByN component in ADS, expecting to see a reduction by 20*log10(N) (N=2 in this case, so -6 dB). What I actually see though are some very weird results. I'm using a Circuit Envelope simulation engine, with noise analysis turned on. To generate the phase noise I use the OSCwPhNoise component. To plot the phase noise I use a phase demodulator and then take 10*log10(0.5*noise**2) for the noise in the phase demodulated node.
The problem is that I'm not at all seeing the -6 dB I expected. Rather, I'm seeing what appears to be a bit "random" results. The longer I let the simulation run, the weirder the results get. The noise seems to be "accumulating" in the divided node. Sometimes I get phase noise much lower (like -50 dB lower) and sometimes I actually get phase noise that's much higher (like +100 dB) in the divided node. Anyone have any clue as to why this is happening?
I'm not really sure if I should include the 2 GHz as an analysis frequency for the Circuit Envelope controller? Even if I include it I get weird results though.
I'm attaching a picture of the schematic and the display window. As you can see the results are what I expect for the undivided phase noise but really strange for the divided node.
Thanks in advance for any thoughts on the matter.
I was trying to simulate phase noise getting divided down by a DivideByN component in ADS, expecting to see a reduction by 20*log10(N) (N=2 in this case, so -6 dB). What I actually see though are some very weird results. I'm using a Circuit Envelope simulation engine, with noise analysis turned on. To generate the phase noise I use the OSCwPhNoise component. To plot the phase noise I use a phase demodulator and then take 10*log10(0.5*noise**2) for the noise in the phase demodulated node.
The problem is that I'm not at all seeing the -6 dB I expected. Rather, I'm seeing what appears to be a bit "random" results. The longer I let the simulation run, the weirder the results get. The noise seems to be "accumulating" in the divided node. Sometimes I get phase noise much lower (like -50 dB lower) and sometimes I actually get phase noise that's much higher (like +100 dB) in the divided node. Anyone have any clue as to why this is happening?
I'm not really sure if I should include the 2 GHz as an analysis frequency for the Circuit Envelope controller? Even if I include it I get weird results though.
I'm attaching a picture of the schematic and the display window. As you can see the results are what I expect for the undivided phase noise but really strange for the divided node.
Thanks in advance for any thoughts on the matter.