strange problem in ML605, using diffectial clock I guess

[syedshan]

Dear all,

I am using ML605 (virtex 6 ) evaluation board. and while learning the differential clock I am facing a strange issue...

I wanted to test the differential clock connection so since it is 20 MhZ, I slow it down to 100 MhZ using clocking wizard


I made a 25 bit counter whose MSB will toggle with 3 Hz freqeuncy, this way I can easily judge if I have done all things right.

Now I connected th 25th bit to the led 0 of the board. It is working perfectly fine, but some other leds are also toggling. they are led 6 and led 7
alsthough I have not mentioned them in my ucf file (following)

# PlanAhead Generated physical constraints 

NET "CLK_IN1_P" LOC = J9;
NET "cnt[24]" LOC = AC22;
NET "rst" LOC = D22;

So I can't understand why is this happening, there must be a reson behind it. I will be really thankful if someone
help me with this. The counter code is as follows, with instantiation of MMCM to lower down clock to 100 MhZ

module cnet(
    input CLK_IN1_P,CLK_IN1_N,
    input rst,
    output reg [24:0] cnt    );

always@(posedge CLK_OUT1)
if(rst)
	cnt <= 25'd0;
	else cnt <= cnt + 1'b1;

//Clock Instantiation
  clk1 pc1
   (// Clock in ports
    .CLK_IN1_P(CLK_IN1_P),    // IN
    .CLK_IN1_N(CLK_IN1_N),    // IN
    .CLK_OUT1(CLK_OUT1));    // OUT

endmodule

Regards,
Shan

 

[Toneski_IP]

My 1st problem with your sample code is that while you don't mention reg[23:0] in your UCF file, you are still outputing these bits. If you dont tell your tools where these connections are to go, the tools will gladly assign them to ANY spare pins you have. And when I say ANY I mean, ANY - I have a feeling that your LED's are - by chance - being driven by some of these bits of your counter.
The funny thing about letting the tools choose which pins are to be driven is that there is every chance that if you re-place and route your design, the toggling LED's could move to other LED's - or stop toggling at all.

You should change your design to only output bit 24 of cnt.

The other thing is that you dont seem to define which pin your CLK_IN1_N is coming from - again, the tools will connect this signal to any ole pin it can find...

Hope this helps..

 

[syedshan]

Thank you for reply,

It seems a logical answer and I am sure the solution lies in it,I will try that, but one question, isn't it obvious that since I have defined the ucf file so the tool should follow that ucf and only assign number of pins defined there and ignoring others that are left undefined (of course it is just what I perceived the PAR tool should have done).

Regarding the other CLK_IN1_N pin, it is a differential clock pair so when I connect the postive pin to J9, the Plan Ahead tool will itself connect it to the H9 ( negative pin connection of Differential clock-pair).
Hence this wont create any non-obvious connection.