Strange LVS error: "Pin Errors for Models"

[jemos]

I've come to a problem in the LVS. In my master cell, MASTER, I've a specific cell, lets call it CHILD. The LVS on the CHILD ends without any error. The CHILD cell in the MASTER layout doesn't have any wire. If I do an LVS it gives me the .lnn with:

.subckt CHILD avC18
...
.ends CHILD

...

.subckt MASTER
...
x|I45 xgnd CHILD
...
.ends

The "Layout / Info, Name" of Pins Mismatch Tool says: "Pin: avC18 Cell: CHILD".

Any idea? I've been trying to solve this problem for hours now. It seems to me that LVS is "connecting" a pin to the CHILD instance and I've no idea why it is doing it....

Thank you for any help.

 

[jemos]

Now I understand. It is related with the fact that the LVS script of this foundry only accepts one pin/net for the NMOS body polarization. I was linking both grounds only outside of the chip, that is not "visible" in the layout...