Strange FSM behavior: it goes straight to "work" state without "wait2work"

[Pavelll]

Strange FSM behavior: it goes straight to "work" state without "wait2work"

Hello friends!
I use FSM in my project and it behaves very strange.

always @(*)
        case (state_global)

        `WAIT : if      (wait2pass) state_next_global = `PASS;
                else if (wait2work) state_next_global = `WORK;
		else		    state_next_global = `WAIT;

        `PASS : if      (pass2wait) state_next_global = `WAIT;

        `WORK : if      (work2wait) state_next_global = `WAIT;


        default : 		    state_next_global = `PASS;

        endcase 

always @(posedge CLK or negedge RSTn) if (!RSTn) state_global<=`WAIT;
        			      else state_global<=state_next_global;

During simulation there is never high ¨wait2work¨ signal but the state machine turns in ¨WORK¨ state. Why does it happen?
Thanks.

 

[andyme]

Re: Strange FSM behavior

FSM has three states, which needs 2-bits to cover all the possible states. I guess one possibility is that only 1-bit is assigned.
BTW, `PASS and `WORK state should add 'else' branch to avoid latch.

Hello friends!
I use FSM in my project and it behaves very strange.

always @(*)
        case (state_global)

        `WAIT : if      (wait2pass) state_next_global = `PASS;
                else if (wait2work) state_next_global = `WORK;
		else		    state_next_global = `WAIT;

        `PASS : if      (pass2wait) state_next_global = `WAIT; 

        `WORK : if      (work2wait) state_next_global = `WAIT;

        default : 		    state_next_global = `PASS;

        endcase 

always @(posedge CLK or negedge RSTn) if (!RSTn) state_global<=`WAIT;
        			      else state_global<=state_next_global;

During simulation there is never high ¨wait2work¨ signal but the state machine turns in ¨WORK¨ state. Why does it happen?
Thanks.

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