[SOLVED] Stopping a countdown timer from 9-0.

Code Verilog - [expand]
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module countdowntimer(SEG,reset,clk);
 
reg [32:0] counter;  
input reset;
input clk;
output [6:0] SEG;
reg [6:0] oSEG;
 
//initial begin
//end
  
always @(posedge clk, posedge reset) begin 
    if(reset) begin
        counter <= 500000000;
        oSEG <= 7'b1000000; 
        end 
    else begin
      if (counter == 0) begin 
            counter <= 500000000;   
            end 
        else begin 
            counter <= counter-1'b1;
            //oSEG <= 7'b0;
            case(counter)
                450000000: oSEG <= 7'b0011000;//9   
                400000000: oSEG <= 7'b0000000;//8 
                350000000: oSEG <= 7'b1111000;//7 
                300000000: oSEG <= 7'b0000010;//6   
                250000000: oSEG <= 7'b0010010;//5   
                200000000: oSEG <= 7'b0011001;//4 
                150000000: oSEG <= 7'b0110000;//3 
                100000000: oSEG <= 7'b0100100;//2
                50000000: oSEG <= 7'b1111001;   //1
                1000: oSEG <= 7'b1000000;   //0
            endcase
            end 
    end
end
 
assign SEG = oSEG;
  
endmodule