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sti stress related issue(overlapping s/d of mosfet)

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nannapaneni

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HI all,
I had a confusion while doing layout.

In schematic tre is a current mirror 2(M1):22(M2).
To had a matching I place them like a matrix 6*4 with 2(M1) at positions say in matrix notation ( A23 and A 34).
And I overlap the 22(M2) s/d regions. Finally placed dummies around matrix.

Is tre any issue like STI(which may change threshold)

Thanks all
-N.KoteswaraRao
 

bhagyasree

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Hi,
I think the matching pattern is not correct.
And u said it to be a current mirror.So u cannnot share the drain of M2 and M22. so u cant even share M22 source/drain.
If u share M22 drain and not sharing M2 drains then there will be sti effect.
Do not share source drain .for current mirror interdigitation pattern is suffieient. do not go for more no of rows as it increses routing complexity.
Hope this will be helpful.
 

nannapaneni

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If I use interdigiation the row length becomes that is why i went for 6x4 matrix arrangement.
If i share M2 S/D and M1 S/D what exactly happens(like change of vt why), do u have any papers can u share the link it will be helpful to me
 

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