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STI and Leakage in cmos

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Jushoraj

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Hi,

Can someone explain me clearly how STI helps to reduce Leakage.
 

erikl

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I think the main reason is limiting the device area resp. (depletion) volume (STI is also called Box Isolation Technique). Leakage current through a blocked junction (at least its generation current part) is proportional to the depleted volume.
 

dick_freebird

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STI only improves leakage relative to predecessor isolation
techniques such as LOCOS. There the large-ish "bird's beak"
(region of tapering oxide thickness, with low quality oxide)
creates a small soft parasitic FET with less than ideal gate
authority over the surface below.

STI makes this more abrupt and can be (not necessarily,
is) a thinner oxide and better quality. However STI also
can add local strain more than LOCOS did. Simply going
STI is not enough, you'd have to engineer the unit process
to get the oxide suitably benign. Which was also true of
LOCOS in the day (edge and/or field implants to keep it
out of the picture electrically).
 

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