stepper motor vhdl codes

[Sweta25]

Hi I am trying to write codes for half step for stepper motor and I am using a clock divider so as I can choose the frequency of the motor. But I am getting errors, any help would be appreciated. Thanks in advance

library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;


entity driver is
port(
clk : in STD_LOGIC;
start : in STD_LOGIC;
Dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end driver;



architecture driver of driver is 
component clkdiv
port
(
mclk : in STD_LOGIC;
clr : in STD_LOGIC_VECTOR(0 downto 0);
clk94: out STD_LOGIC
); 
end component; 
signal clk94 : STD_LOGIC; 
begin
U1 : clkdiv
port map
(
mclk => mclk, clr => clr, clk94 => clk   <--------- ERROR
); 

process ( clk, start)is 
variable m: std_logic_vector ( 2 downto 0);
begin 
if (start ='1')then
if (rising_edge (clk)) then
m:= m +1 ;
end if;
end if;
case m is 
when "000" => Dout <= "1000";
when "001" => Dout <= "1100";
when "010" => Dout <= "0100";
when "011" => Dout <= "0110";
when "100" => Dout <= "0010";
when "101" => Dout <= "0011";
when "110" => Dout <= "0001";
when others => Dout <= "1001";
end case;
end process;
end driver;

Codes for clk div

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;


entity clkdiv is
port(
mclk : in STD_LOGIC;
clr : in STD_LOGIC_VECTOR(0 downto 0);
clk94: out STD_LOGIC;
clk : out STD_LOGIC_VECTOR (2 downto 0)

);
end clkdiv;


architecture clkdiv of clkdiv is 
signal q: STD_LOGIC_VECTOR (23 downto 0); 

begin


process (mclk ,clr(0))
begin 
if clr(0)= '1' then 
q <= X"000000" ;
elsif mclk 'event and mclk = '1' then 
q <= q + 1;
end if ;
end process;
clk(0)<= q(0); 
clk(1)<= q(1);
clk(2)<= q(21);
clk94 <= q(19);


end clkdiv;

errors:

# Error: COMP96_0078: driver.vhd : (51, 10): Unknown identifier "mclk".
# Error: COMP96_0078: driver.vhd : (51, 23): Unknown identifier "clr".
# Error: COMP96_0133: driver.vhd : (51, 10): Cannot find object declaration.
# Error: COMP96_0133: driver.vhd : (51, 23): Cannot find object declaration.
# Error: COMP96_0413: driver.vhd : (51, 37): Actual of mode 'in' cannot be assigned to formal "clk94" of mode 'out'.
# Error: COMP96_0104: driver.vhd : (51, 2): Undefined type of expression.
# Error: COMP96_0104: driver.vhd : (51, 16): Undefined type of expression.
# Compile failure 7 Errors 0 Warnings Analysis time : 16.0 [ms]

 

[sharath666]

mclk and clr are not defined. You are assigning clk which is an input port to clk94 from clkdiv which is an output. You cannot do that...

 

[ads-ee]

Considering that you are making the poor design decision to generate a clock from the output of a counter, you should at the very least synchronize the inputs to the FSM driven by that clock.

 

[kishornakul]

Re: stepper motor vhdl codes

Check your clkdiv.vhd code. There is port mismatch, it means "clkdiv.vhd has 2 input,2 output but in driver.vhd component declaration only 2 input and one output. Then mclk and clr is not declared anywhere in driver.vhd so check it
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