# [SOLVED]std_logic_vector to integer

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#### Ivan-Holm

##### Member level 5
I would like to know how to convert from std_logic_vector to integer this is my code:

please show the conversion in an example

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library IEEE;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

entity PWM is
Port (           PWMOUT : out  STD_LOGIC;
CLK_PWM : in  STD_LOGIC;
--DC_Counter_PWM : in integer range 0 to 10
DC_Counter_PWM : in STD_LOGIC_VECTOR (3 downto 0)
);
end PWM;

architecture Behavioral of PWM is

begin
process (CLK_PWM)
variable T : integer range 0 to 10;
variable counter : integer range 0 to 10;
begin

Counter <= to_integer(unsigned(DC_Counter_PWM));    -- ??

if CLK_PWM'event and CLK_PWM='1' then
if (T >= Counter) then
PWMOUT <= '0';
T := T+1;
elsif (T < Counter) then
PWMOUT <= '1';
T := T+1;
end if;
end if;
end process;
end;

#### Alexium

##### Full Member level 2
Counter := conv_integer(DC_Counter_PWM);

#### FvM

##### Super Moderator
Staff member
You are using two numeric libraries, that should be used mutually exclusive: the official IEEE.numeric_std and legacy IEEE.STD_LOGIC_ARITH, originally introduced by Synopsis before numeric_std came out. IEEE.STD_LOGIC_UNSIGNED is another Synopsys library, that allows arithmetic operations on std_logic_vector without defining unsigned objects explicitely. It's still used in some vendor IP, but mainly bringing up bad coding style.

As to_integer is the numeric_std type conversion variant, you should simply remove the 2nd and 3rd library reference. If you check the operation of your code in a hardware implementation, you'll notice that T will count up to 15, although it has a range constraint. In a simulation, you will get an error. Thus you should explicitely code the the rollover from 10 to 0.

Code:
IF T >= 9 THEN
T := 0;
ELSE
T:=T+1;
END IF;
P.S.: conv_integer() is in contrast the STD_LOGIC_ARITH conversion function.

#### Alexium

##### Full Member level 2
I have found IEEE.STD_LOGIC_ARITH to satisfy all my needs for arithmetical operations on STD_VECTORs, and IEEE.numeric_std, on contrary, only gives me trouble. But I always include both, never had problems with it...

---------- Post added at 23:18 ---------- Previous post was at 23:15 ----------

This is the set of libraries I always include to my modules:

use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;

I'm not sure how smart is it, though

#### std_match

I have found IEEE.STD_LOGIC_ARITH to satisfy all my needs for arithmetical operations on STD_VECTORs, and IEEE.numeric_std, on contrary, only gives me trouble. But I always include both, never had problems with it...

numeric_std can do everything you need, but you have to learn to use it!
It is a different coding style, more strict, but you know exactly what will happen. You can't do "+1" on a std_logic_vector etc. but that is just a sloppy coding style. If you want to do "+1", declare the signal/port as unsigned or signed. If you instead do it with casts/conversions, the code will be ugly.

You can not convert directly between std_logic_vector and integer.
You must go via unsigned or signed, which makes sense.

With the non-standard std_logic_arith etc. you can not mix unsigned and signed in the same source file.

Please try to use only numeric_std! We have that as a mandatory rule at work, and that is not a problem. It helps to avoid problems.

#### permute

IIRC, VHDL2008 is finally adding the convenience functions to numeric_std. I find numeric_std to be too academic. I don't think it adds anything to say "here's a signal, oh and I did an addition once. No where in the code do I interpret the result as signed/unsigned/offset or any type of number. Still it is vital for you to know that this is an unsigned number. My telling you that this is specifically an unsigned number is intended to make it clear that I don't use in in that manner."

#### TrickyDicky

I have found IEEE.STD_LOGIC_ARITH to satisfy all my needs for arithmetical operations on STD_VECTORs, and IEEE.numeric_std, on contrary, only gives me trouble. But I always include both, never had problems with it...

---------- Post added at 23:18 ---------- Previous post was at 23:15 ----------

This is the set of libraries I always include to my modules:

use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;

I'm not sure how smart is it, though

The problem is here is that std_logic_arith and numeric_std both declare signed and unsigned types, so by including both libraries you make your life more difficult, because you have to qualify which type you mean every time you declare a signals:

signal a : unsigned(7 downto 0); --you cant do this, because unsigned is declared twice, so both are invisible directly.

signal b : ieee.numeric_std.unsigned(7 downto 0);
signal c : ieee.std_logic_arith.unsigned(7 downto 0); --you've specified which one you want. Also remember that b and c are not the same type.

---------- Post added at 07:58 ---------- Previous post was at 07:55 ----------

IIRC, VHDL2008 is finally adding the convenience functions to numeric_std. I find numeric_std to be too academic. I don't think it adds anything to say "here's a signal, oh and I did an addition once. No where in the code do I interpret the result as signed/unsigned/offset or any type of number. Still it is vital for you to know that this is an unsigned number. My telling you that this is specifically an unsigned number is intended to make it clear that I don't use in in that manner."

Kind of, and not really.
VHDL2008 adds the packages numeric_std_signed and numeric_std_unsigned which are just repackaged std_logic_signed/unsigned.

What numeric_std allows is signed and unsigned arithmatic in the same file, which you cannot do with std_logic_signed/unsigned.