Ivan-Holm
Member level 5

I would like to know how to convert from std_logic_vector to integer this is my code:
please show the conversion in an example
please show the conversion in an example
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 library IEEE; USE ieee.std_logic_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.all; entity PWM is Port ( PWMOUT : out STD_LOGIC; CLK_PWM : in STD_LOGIC; --DC_Counter_PWM : in integer range 0 to 10 DC_Counter_PWM : in STD_LOGIC_VECTOR (3 downto 0) ); end PWM; architecture Behavioral of PWM is begin process (CLK_PWM) variable T : integer range 0 to 10; variable counter : integer range 0 to 10; begin Counter <= to_integer(unsigned(DC_Counter_PWM)); -- ?? if CLK_PWM'event and CLK_PWM='1' then if (T >= Counter) then PWMOUT <= '0'; T := T+1; elsif (T < Counter) then PWMOUT <= '1'; T := T+1; end if; end if; end process; end;