std_logic_vector and signed/ unsigned mapping

[rameshrai]

Hi,

The system ports are declared std_logic_vector, it's subsystem has its port signed and unsigned type. Yet there is mapping of the ports between the system and subsystem although they have different type declaration.

does it imply there is automatic conversion from std_logic_vector to unsigned/ signed type?

thanks

 

[TrickyDicky]

there is no automatic conversion, you will have to do it in the code. It is free from a hardware POV, but without it, it is illegal VHDL.

As signed/unsigned and std_logic_vector are closely related types, a type conversion is all that is required:

some_slv <= std_logic_vector(some_unsigned);

 

[rameshrai]

the codes were successfully compiled but the simulator should show this in error, isn't this?

 

[TrickyDicky]

you havent shown the code, so I cannto comment on whats happening.

 

[rameshrai]

the input did match, somehow i got it wrong.

i have signed input as main system input. Should it be changed to std_logic_vector(using converter afterwards)? because it is said that it is good practice to have the main system inputs as std_logic_vector.

Also i don't understand the following code example:

package pkg is 
type sel_type is(apple,banana,mango);
end;

entity encoder is
    Port ( 
	       sel:in sel_type;
           ....
		   ....
		   );
end encoder;

architecture Behavioral of encoder is

begin
  process(sel)
begin

case sel is
			when apple =>
 							out1 <= '0';
 							out2 <= '0';

			when banana =>
 							out1 <= '1';
 							out2 <= '0';
			when mango =>
 							out1 <= '1';
 							out2 <= '1';

The sel is an input of type sel_type, what is the input value we are passing in this case, string? like apple? i am a beginner

how can i recode above encoder without using the package? by removing the package.

thanks

 

[TrickyDicky]

It's not always neccesary to use only std_logic_vector. The important thing is to ensure you can map individual bits to specific pins. So std_logic_vector, unsigned and signed should work fine with modern tools. Older versions scoffed a bit at non-std_logic_vector ports, so some companies insist on std_logic_vector only at top level, but its the same thing. What wouldnt be acceptible at the top level (internally is fine) is things like integer or your own custom types (like sel_type above) because you cannot access the individual bits of the signal.

In the code you posted, the value you have to pass in is a sel_type. String is not a sel_type, its a string. If these custom types are used, you must include the package in your code. To re-code without the package, you will be a bit stuck, as I assume you will have to interface it somewhere, unless you're trying to remove sel_type altogether?

Why not post some real code and give us an idea of what you're trying to do...

 

[rameshrai]

thanks i think i got it for now, the codes are somebody else so i better not post here, although it would helped the discussion here

thanks again