Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
No matter how many levels, you want to impose the
fewest routing barriers. Sometimes you will see poly
used as local interconnect (or crossunders), even,
although this is frowned upon generally. Even a small
bit of (say) metal2 in a few standard cells can have a
ripple effect making a lot of lines dodge it, and each
other, adding to both chip and routing-wall-time bloat.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.