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[Jerry Yau]

Hi sir,
I have a resistor which 2 terminals are shorted together shown in follow picture :

　　　　　　　　　　　　　　　　　resistor
　　|----------------------------^^^^^^^^^--------------------|
---|---------------------------------------------------- -----|
　terminal 1　 A wire to short resistor　　　　　　　　　terminal 2

Ans I implement it in layout as following:

　
　　 metal1　　　nwell　　　metal1　　　　nwell　　　metal1
　　l------------=========--------------==========----------l
　　l　wire1　　resistor 1　　wire2　　　resistor 2　wire3 　l
---l-------------------------------------------------------l
　terminal 1　　　　　　　　　metal1　　　　　　　　　terminal 2

My calibre lvs rule file has following settting :
LVS FILTER UNUSED OPTION B C D E F G H I J K O RC LAYOUT
LVS FILTER UNUSED OPTION F G H I J K O SOURCE
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES

So I want calibre can combine two nwell resistors to one resistor which 2 terminals are shorted by metal1 in order to match the schematic.
After runing lvs process, calibre said this 2 resistors are parallel not series and then report there is a missing net named wire2 in schematic.

How can I resolve this problem if we can't modify layout?

Thanks.