Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Static timing on latch based design

Status
Not open for further replies.

no_mad

Full Member level 5
Joined
Dec 10, 2004
Messages
271
Helped
30
Reputation
60
Reaction score
11
Trophy points
1,298
Location
Naboo
Activity points
2,489
Hi

People always tell me to avoid using latch in a design. This is due to the difficulties tht I will face later during my static timing analysis.

So far, I havent done the STA on latch based design before. Now, can someone pleeease enlighten me.

Why is it so hard to do STA on latch design?? What are the difficulties and the right method to do STA on latch based design??


Thanx in advance
no_mad
 

I suggest u first understand time stealing/borrowing concept in a latch based design.
the basic idea is – one logical partition utilizes
a portion of time allotted to the next
partition.

its hard to analyse whether the designer has intended to use timeborrowing in a latch based design. so sta is difficult.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top