Static Timing Analysis

[srrameshonline]

How to perform Static Timing Analysis using Synopsys Prime Time?
when i try to find STA i am getting the following error message
"No constrained paths"
I need to find the worst case delay in a circuit sat alu4 or c7552,c3540 etc.
Can anybody please help me??

 

[sharath666]

You don't seem to have provided any constraints for your design. That is the reason the tool throws this message.
If you don't provide any constraints, how will a timing tool know what is expected of it?

 

[srrameshonline]

thanks for your reply sharath.but where exactly in the prime time tool to provide this constraint .
If you have any video lecture links or pdf kindly send me the link

 

[jigs047]

hi , after reading the netlist you can provide the required constraints .

 

[sharath666]

U can use the synthesis constraints itself as the base. Just source this constraints file during the primetime run...