# Static Timing Analysis

Status
Not open for further replies.

#### jayakumarjay

##### Junior Member level 3
set_clock_transition

can anyone tell me how to select set up time, hold time , rise time , fall time.

is it depend on the frequency of the design or the technology library

do we need to give transition time for the output pins also

#### eda_wiz

static timing analysis setup concept

setup and hold time depends on the library FF cell.
risetime and fall time depends on capacitance of pins and frequency..

transition time is usually specified for inputs ..(dont know about outputs)

#### linuxluo

##### Full Member level 6
transition time + static timing analysis

hi,
the transition time of output pin is calculated based on the input of the cell and the load of the output pin.

#### lailiya

##### Newbie level 6
set_max_transtion set_input_transtion

you can set the transition time for the input pins, the command is: set_input_transtion input_ports
you also can constrain the transition time for the output pins, the command is:
set_max_transtion outpout_ports
Design Compiler will select correct cells to meet the constrain

#### dinnu

##### Newbie level 4
Hello
can anyone tell me how to select set up time, hold time , rise time , fall time.
This is basically depends on the technology you are targetting you need to see the basic element
there its given min/max/typical
based on that you can choose like eg, for taget technology of 0.18u the mux set up is 0.2 ns
etc

do we need to give transition time for the output pins also

yes we do need to give that
how the user of chip will understand that when i have to capture the signal

dinu

#### xmizi

##### Member level 1
for the transition time(slew), usually you dont need to give it out directly, for the input you just specify a driving cell or a drive strength, for the output you just specify a loading capacitance, that's it.

#### maxsnail

##### Member level 5
set_clock_uncertainty [expr $cfg_clk($clk_rooteriod)/12.0] -setup $clk_root set_clock_uncertainty [expr$cfg_clk($clk_rooteriod)/10.0] -hold$clk_root
set_drive 0 $clk_root set_dont_touch_network$clk_root
set_clock_transition -rise -max 3 $clk_root set_clock_transition -rise -min 1$clk_root
set_clock_transition -fall -max 3 $clk_root set_clock_transition -fall -min 1$clk_root
create_generated_clock -source XIN32K -multiply_by 1 [get_object_name [find pin crystal_Oscillator32K/clk_osc]]

#### tochaHCM

##### Full Member level 1
it's not simple so we can show you in few line. your question is too general. Read the manual and tutorial of primetime in SOLD

#### vijay43

##### Newbie level 6
Set up time and hold time are defined in the library and it varies with the size of the flop.... we can give the input slew and it is also dependent on the input capacitance... the output slew is dependent on the output capacitance.. i mean load....

mail4idle1

### mail4idle1

Points: 2

#### dftrtl

##### Banned
Setup time and Hold time comes from the libraries what you are using.

mail4idle1

Points: 2