static timing analysis at the module level

[tariq786]

Hi friends,

I want to know how one can do static timing analysis at the module or block level?

If i have a design that contains many modules, is it possible to find the worst case path in each module or block? Note that some of the modules could be purely combinatorial.

Please share your thoughts with me. If you could point out some tutorials, that would be great


Thanks

 

[birdy123]

Following link might help you...

STA using EDA tool part1

SAT using EDA tool Part2

Hierichal Design part 1

Hierichal Design part 2