Static power of two stage amplifer design in cadence

[electronics20]

Dear all
I am designing a two stage amplifier by TSMC 130 nm CMOS tech. How to measure static power of this opamp in cadence?
Thanks

 

[kpc]

Hi,
You should have a voltage source in your device (i.e., Vdd as a DC power source). Simply measuring the current that this source gives (let's say it is idd), you can calculate the total static power of the opamp by calculating vdd*idd.

 

[dick_freebird]

If static power also means output-unloaded (DC) then
simple supply current*voltage measurement. If there is
any current running outside the vdd-vss current loop
then it needs to be figured, current path and drop along
it, internal to the amplifier. Your Pdiss might be less than
a raw (i(vdd)*(vdd-vss)) calculation if some runs from
vdd to out, now you have something like
(i(vdd)-i(out))*(vdd-vss)+i(out)*(vdd-vout) if the output
is sourcing current; different if sinking current, then it's
(i(vdd)-i(out))*(vdd-vss)+i(out)*(v(out)-vss). And there
may be additional adders, like the dissipated power in the
bias rack which is perhaps fed current-mode and contributes
i(bias)*(v(bias)-v(vss)) within the amplifier. The sourcing
loss i(bias)*(v(vdd)-v(bias)) ought to be accounted for
elsewhere.