State machine question

[phoenix_pavan]

A mealy –type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the state machine be synthesized correctly?

A moore –type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the state machine be synthesized correctly?

 

[SWINI]

even though the signals are declared in the sensitivity list they can be freely used in the process...
therefore the state machine can be synthesised normally