state machine Or Behavioural

[research_vlsi]

Hi friends,

I am writing a code for functionality of USART. For Asyn part i wrote a code in Behavioral, But the same, is possible to design using state machine also,

Which approach is best. Either FSM or Behavoiural ?

Or we want to see the Hardware after synthesis ?

Thanks & Regards

 

[nmurthy]

To my knowledge the FSM approach will be good one
so carry on with FSM

 

[rakesh_aadhimoolam]

It is always a good practice to go through the FSM modelling

good luck

 

[research_vlsi]

Thank you people..

 

[dragonight_x]

I agree with nmurthy and rakesh …….. the FSM is always a better approach so go for it & good luck

 

[vcnvcc]

Hi research_vlsi,

I have doubt here as far as USART's synchronous part is concern, how u'll test it? i mean say u'll test it on prototype fpga board. And testing of Asynch part i know. But how to test Synch part of usart on board......

thanks in adv....