State machine coding problem?

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dd2001

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How to write a state machine to do following:

reg [1:0] current, next


....

if (yes)
next = current + 1'b1; //state -- A0

else
next stay in A0 ; //how to implimented this ????


.....
 

refer to Xilinx Synthesis Technology (XST) user guide page 196 to page 210 .. It's very useful and have detialed examples
 

in which HDL u want to write
genral rule is that u can associate the counter and that increase at every clock cycle and check the condition at every count

ashish
 

Basic example.. hope it helps in some way..

jelydonut

// Update the current state
always @(posedge rclk or posedge rst)
if(rst)
receivefsm = RIDLE;
else
receivefsm = next_receivefsm;


// FSM next state and decodes
always @(receivefsm or sin or rxdsampletime or startbitdet or
rxbitcntdone or pen or rxdbittime or rxdlatchtime)
begin
setrxbufregld = 1'b0;

case(receivefsm)
RIDLE :begin
if(startbitdet)
next_receivefsm = RECEIVING;
else
next_receivefsm = RIDLE;
end
more cases...

endcase......
 

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