bazook
Newbie level 5
Hi,
i am newbie in VHDL and when i started with designing some questions come to mind:
1. I've found out that using signs '>' or '<' isn't a good practise. What is better way to compare two vectors, especially in 'if' ?
2. What i should avoid if i would like to write in RTL. I know that it shouldn't be sequential so 'process' and 'after' cannot be. Something important else? 'Process' is in RTL undesirable always?
i am newbie in VHDL and when i started with designing some questions come to mind:
1. I've found out that using signs '>' or '<' isn't a good practise. What is better way to compare two vectors, especially in 'if' ?
2. What i should avoid if i would like to write in RTL. I know that it shouldn't be sequential so 'process' and 'after' cannot be. Something important else? 'Process' is in RTL undesirable always?