Standby leakage Power Reduction using Dual Vth

[rama_227]

hi,
i am doing ''Standby leakage Power Reduction using Dual Vth in Domino Logic Circuits" project, i need some information about this.

 

[eda_wiz]

Message is unavailable.

 

[rama_227]

i want code any one language like c,vhdl 7or verilog

Added after 18 seconds:

i want code any one language like c,vhdl or verilog

 

[eda_wiz]

vhdl code for leakage power reduction!!!. hmmm I think u should try reading some basics....

VHDL,Verilog describes hardware. Multi Vth cells are selected during synthesis by the synthesis tool.

I wonder whether you are asking for the C-code for selection of Multi-Vth cells for synthesis. there is very less chance of getting such a c-code. It will be there with EDA biggies like Synopsys,cadence,MG.

What exactly you want to do as project?

 

[rama_227]

any one of the laguage i want code please help me