standard cell verifcation

[research235]

Hello all

I have some 800 standard/library cells . I want to do the physical verifation(DRC/LVS) using calibre. Is it possible to check for all the cells at one run .
I have all the cells as a signe gds2 file .. and a single cdl file with no single top level cell .. can soem one help me with is ..


thank you

Suresh

 

[avimit]

Hi,
The way I have done it in the past is, by creating a top level with all library cells instantiated in it. I dont know if it works without doing a top level.
Kr,
Avi
http://www.vlsiip.com

 

[research235]

yeah ..


Thanks a lot i wll try that way ..

suresh

 

[research235]

helllo avimit.

Could you tell me how to create a top level ..


suresh

 

[avimit]

Hi,
It was long time ago, when I did it last time. May be I will give it a try.
Make a verilog file.
Instantiate all cells in it, short each input of each cell except the clock pin and make this net as an Input Port.
Short all clock pins of each cells, make it another input port
Then make a bus of all output ports.

This is your top level.
Read it in your floorplan tool to get a cdl, and pnr it to get a layout.
then run DRC/LVS
kr,
Avi
http://www.vlsiip.com

 

[kumar_eee]

It is possible by using Calibre.. U need to run it in batch mode...