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standard cell library design

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novicevlsi

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12 track std cells

Hi

i want to develop a standard cell library
for .13u/.09u technology.

can anyone guide me on this .

1) what tools are required; i have tools for
schematic drawing, spice simulation, layout drawing, drc/lvs, netlist extraction; all from silvaco's iccad suite.

2) please explain clearly step by step method of making a standard cell library.


thanks

regard

novice
 

ahmad_abdulghany

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standard cell track

You want to design standard cell of what exactly?!?!

Notice also, it's not as easy job as to simply state forward steps to make such library, you have to be robus in analog IC design, VLSI design, also, you would better to use more stronger simulatro and design tools rather than Pspice, Cadence ICx is a good example of that tools,

Regards,
Ahmad,
 

linuxluo

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build standard cell with parameter

hi,
it's a tough job.
you have to provide liberty model, lef model, simulation model, etc.
for liberty model you can use cadence signalstorm-lc , for lef model, you can use cadence abstrct, for simulation model, I dont know any auto eda tools.
 

jackson_peng

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9-track cell library

forget it. you can never build it on your own.

some tools are available for cell characterization, like cadence voltage storm, and synopsys star-mtb...
 

cdic

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what is 9-track standard cell library

It's doable, the thing is that how to qualify them, if you have no chance to tapeout with it, no point to work on it. Unless you just want to go through the flow.
 

semi_jl

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It's really a tough job, and it will be modified a few times after you tapeout with it.
 

archillios

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cell library design

I know synopsys provide a tool which can extract timing model from layout.
But, I think tools is not critical, the most important is how can you verify your library. Unverified through silicon success does not mean too much.
 

woodyplum

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internal power of a standard cell

SNPS have tools can do it for you from the spice level, check it in SOLD
 

ls000rhb

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aoi standard cells design

i think this job maybe donw by the foundry or big IP provider,you can do it ,but the bussiness value maybe noting .!!!!
 

singu31

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internal power for characterizer

Hi
I am working on creating a standard cell library. I am attaching a conference paper done by me which explains the steps involved in creating a standard cell library.

If u have any questions pls mail me.
 

jarodz

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standard cell internal power

Hi singu31,

Can you share the related scripts used to do characterization?

Sincerely,
Jarod
 

joe2moon

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track standard cells

Nangate Cell Compiler (https://www.nangate.com/index.php?option=com_content&task=view&id=38&Itemid=58)
==============
Compiling the optimal set of individually optimized cells for a given design or functional block, the target design is optimized in terms of power, performance and area.

Features:
======
- 1) Rich set of CMOS logic cell generators with programmable drive strengths:
-- Buffers (inverting, non-inverting, clock)
-- Boolean combinatorial (AND, OR, NAND, NOR, AOI, OAI, OA, AO, MUX)
-- User-defined complex gate based on equation input
-- Arithmetic (XOR, XNOR, full-adder, half-adder)
-- Sequential (Lath, clock-gater, D-flip/flop with any optional combination of scan, set and reset)
-- Miscellaneous (tie cells, filler cells, antenna)
- 2) Fully automated layout topology generation using advanced genetic optimization algorithms that minimize cell area and parasitic effects. Optimization strategies include:
-- Optimal cell input sequencing
-- Optimal diffusion strip layout
- 3) Transistor netlist synthesis with built-in transistor sizing algorithms and override options
- 4) User-definable topology generators with support of advanced parameterized set of layout primitives:
-- Contact and contact arrays
-- Single, L-shaped and folded transistor configurations
- 5) Advanced proprietary compaction engine
-- Adaptive topology-driven compaction strategies
-- Full design rule support for advanced CMOS processes
- 6) Circuit and layout verification
-- Built-in formal verification of circuit and layout vs. specification
---------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Nangate Cell Characterizer (https://www.nangate.com/index.php?option=com_content&task=view&id=36&Itemid=56)

Features:
======
- 1) Spice simulations through Nangate Library Manager controls
- 2) Built-in extraction
- 3) Automatic Spice deck generation
-- Built-in Spice simulator as well as interface to customer's industry-standard Spice simulators
-- Support for results correlation reporting
- 4) Accurate input state-dependant characterization of cell parameters as function of cell load and input transition time:
-- Timing: propagation delay, output transition time, setup/hold, recovery, pulse width, no-change time
-- Power: cell internal static and dynamic power
-- Input capacitance
-5 ) Utilizes nonlinear device model for delay and internal power models using two-dimensional lookup tables
-6 ) Built-in extensive stimulus, results and model validation
-7 ) Shared database model with Nangate Library Manager and Nangate Cell Compiler tools for seamless interface
- 8) Alternative input format options include GDSII or Spice circuit netlists
-9) Flexible datasheet generator
- 10) Intuitive GUI with wizard and extensive configuration options for characterization parameters as well as graphical progress monitoring
- 11) Full batch mode support
 

joe1347

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Re: Nangate Cell Compiler

joe2moon said:
Nangate Cell Compiler (h**p://www.nangate.com/index.php?option=com_content&task=view&id=38&Itemid=58)
==============
Compiling the optimal set of individually optimized cells for a given design or functional block, the target design is optimized in terms of power, performance and area.

Features:
======
- 1) Rich set of CMOS logic cell generators with programmable drive strengths:
-- Buffers (inverting, non-inverting, clock)
-- Boolean combinatorial (AND, OR, NAND, NOR, AOI, OAI, OA, AO, MUX)
-- User-defined complex gate based on equation input
-- Arithmetic (XOR, XNOR, full-adder, half-adder)
-- Sequential (Lath, clock-gater, D-flip/flop with any optional combination of scan, set and reset)
-- Miscellaneous (tie cells, filler cells, antenna)
- 2) Fully automated layout topology generation using advanced genetic optimization algorithms that minimize cell area and parasitic effects. Optimization strategies include:
-- Optimal cell input sequencing
-- Optimal diffusion strip layout
- 3) Transistor netlist synthesis with built-in transistor sizing algorithms and override options
- 4) User-definable topology generators with support of advanced parameterized set of layout primitives:
-- Contact and contact arrays
-- Single, L-shaped and folded transistor configurations
- 5) Advanced proprietary compaction engine
-- Adaptive topology-driven compaction strategies
-- Full design rule support for advanced CMOS processes
- 6) Circuit and layout verification
-- Built-in formal verification of circuit and layout vs. specification
---------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Nangate Cell Characterizer (h**p://www.nangate.com/index.php?option=com_content&task=view&id=36&Itemid=56)

Features:
======
- 1) Spice simulations through Nangate Library Manager controls
- 2) Built-in extraction
- 3) Automatic Spice deck generation
-- Built-in Spice simulator as well as interface to customer's industry-standard Spice simulators
-- Support for results correlation reporting
- 4) Accurate input state-dependant characterization of cell parameters as function of cell load and input transition time:
-- Timing: propagation delay, output transition time, setup/hold, recovery, pulse width, no-change time
-- Power: cell internal static and dynamic power
-- Input capacitance
-5 ) Utilizes nonlinear device model for delay and internal power models using two-dimensional lookup tables
-6 ) Built-in extensive stimulus, results and model validation
-7 ) Shared database model with Nangate Library Manager and Nangate Cell Compiler tools for seamless interface
- 8) Alternative input format options include GDSII or Spice circuit netlists
-9) Flexible datasheet generator
- 10) Intuitive GUI with wizard and extensive configuration options for characterization parameters as well as graphical progress monitoring
- 11) Full batch mode support



Any opinions based on past experience regarding NANGATE? I'm also looking to create a .lib file for synthesis from an existing set of standard cells (gds2 and schematics) in a somewhat older technology. Signalstorm (Cadence) seems to be another (or the only) alternative out there.
 

liangshao

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Hi, singu31, any opinion about how to select the 7 points of input skew and output load?
 

kumar_eee

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Can anyone explain me about 9 track or 13 track library?... Which is better & what are the advanteges?..
 

eternal_nan

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singu31, thanks for that paper, it is very useful!

Kumer_eee, libraries with a higher number of horizontal tracks occupied generally result in higher are and higher performance designs. There are two major issues at play here:
- Drive strength
- Routability: the taller cells are less crouded and generally much easier to route with - resulting in generally shorter, lower RC wires.
 

nav_vlsi

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i do agree with eternal_nan,
9 track - better from area perspective
13 track - better from speed perspective

i would like to add one more query, on what basis track height is decided ? , to be more specific, 13 track and 14 track both will give better speed , in such a case what are the factors we must consider in choosing the track height?

one more query friends, consider a case like this, we have already completed a block with 9 track std cells @ 400Mhz, now in the next version of design we want to move to 415Mhz for same block, how to arrive at track height ?
 

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