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Standard cell layout basic

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ABwag

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In cmos layouts we draw poly silicon gate to extend over diffusion or active region.The reason i have searched is that if we do not extend the poly silicon then we might end up with source and drain short circuited.

My question is : The source and drain are separated by channel so how can they be short circuited practically? If any body knows the reason and can help me correlate practically it will be helpful

if someone has a different answer kindly notify.

Poly end cap.PNG
 
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dick_freebird

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The gate poly is a "hard mask" in self aligned CMOS and
you are failing to mask out N+ in the active*!poly region,
making a resistive connection ("short" is a matter of
perspective, probably 5-10 ohms as drawn but how valid
is the cartoon anyway?).
 

ABwag

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The gate poly is a "hard mask" in self aligned CMOS and
you are failing to mask out N+ in the active*!poly region,
making a resistive connection ("short" is a matter of
perspective, probably 5-10 ohms as drawn but how valid
is the cartoon anyway?).
The cartoon is just to demonstrate the question and scenario.

And regarding your answer : fabricating poly and implantation of N+ regions uses two different set of mask . So after fabricating poly ( it helps in self aligning ) , and after that when we are creating source and drain is the poly region protected by the mask used when ion implantation is done?? If its protected then there is no chance of dopant in that region which will result in a short..tell me where i am going wrong.
 

dick_freebird

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You shoot N+ after poly is laid over active (thin ox) and the
gate poly tends to be not-masked for this step, because you
want the gate doped too. Your field ox and your poly both
hard-mask the implant. The open active cut and the bare
poly both receive the implant. This is the norm. N+ mask is
grossly oversized and does not figure into the actual pattern
that results.
 
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    ABwag

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