Standard cell design and design rules

[Yarrow]

Hi,

I am designing some standard cells in 65 nm and I was wondering if it is normal to design standard cells using minimum design rules or DFM rules?

My thought is that one would like to make the standard cells as compact as possible, but to do this one violates the recommended design rules. As I understand it, the recommended design rules are there in order to reduce the possibility of shorts, avoid high RC in contacts/vias, etc.

Is anyone familiar with were I can find yield information when it comes to usage of minimum design rules vs. recommended design rules? For example, what kind of yield can I expect from 30k standard cells designed using minimum design rules..

By the way, I am only doing a prototype run with 50k+ gates.

Appreciate all the input I can get..
Yarrow

 

[dick_freebird]

I don't know anything about what smart guys in advanced nodes
are doing, but in my line I tend to stick with what you might call
"DFM" rules. Like no FET with less than two contacts per S or D,
in some flows making every via a doublet (if via chain yield is a
production issue, which is often seems to be during development)
and so on. But other folks with other values might be more litho
aggressive, and let the manufacturing poor bastages figure out
how to yield it.

Foundry ought to be able to give you certainly a D0 number,
but probably could (not to say, will) give probe yield numbers
for some circuits of similar form & size & production flow. The
yield is not really estimable from your design's relation to rules,
alone - the foundry's capability against those rules matters more.

 

[Yarrow]

Thank you for the reply.

Typically, I used "DFM"-like approach in the past. However, since I am optimizing for area this time around. I guess I will use minimum rules, but avoid them whenever I can.

Hopefully since this is a prototype run it wont have a significant impact.