Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Standard cell design and design rules

Status
Not open for further replies.

Yarrow

Member level 2
Joined
Jan 15, 2009
Messages
49
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Location
Norway
Activity points
1,699
Hi,

I am designing some standard cells in 65 nm and I was wondering if it is normal to design standard cells using minimum design rules or DFM rules?

My thought is that one would like to make the standard cells as compact as possible, but to do this one violates the recommended design rules. As I understand it, the recommended design rules are there in order to reduce the possibility of shorts, avoid high RC in contacts/vias, etc.

Is anyone familiar with were I can find yield information when it comes to usage of minimum design rules vs. recommended design rules? For example, what kind of yield can I expect from 30k standard cells designed using minimum design rules..

By the way, I am only doing a prototype run with 50k+ gates.

Appreciate all the input I can get..
Yarrow
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,352
Helped
2,138
Reputation
4,281
Reaction score
2,003
Trophy points
1,393
Location
USA
Activity points
58,908
I don't know anything about what smart guys in advanced nodes
are doing, but in my line I tend to stick with what you might call
"DFM" rules. Like no FET with less than two contacts per S or D,
in some flows making every via a doublet (if via chain yield is a
production issue, which is often seems to be during development)
and so on. But other folks with other values might be more litho
aggressive, and let the manufacturing poor bastages figure out
how to yield it.

Foundry ought to be able to give you certainly a D0 number,
but probably could (not to say, will) give probe yield numbers
for some circuits of similar form & size & production flow. The
yield is not really estimable from your design's relation to rules,
alone - the foundry's capability against those rules matters more.
 
  • Like
Reactions: Yarrow

    Yarrow

    Points: 2
    Helpful Answer Positive Rating

Yarrow

Member level 2
Joined
Jan 15, 2009
Messages
49
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Location
Norway
Activity points
1,699
Thank you for the reply.

Typically, I used "DFM"-like approach in the past. However, since I am optimizing for area this time around. I guess I will use minimum rules, but avoid them whenever I can.

Hopefully since this is a prototype run it wont have a significant impact.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top