Standard cell 1X driving strength, gate sizing, delay

[rain_181914]

Dear all,

I 'm doing standard cell of library.
Different gates have different gate sizing that will satisfy systhsis request.

For all types of driving strength in standard cell, I 'm no idea how to decide the Normal(1X) condition.

e.g.
----------------------------------------------------------------------------------------
Driving Strength Low(0.4X) Normal(1X) power(2X) Triple(3X)……
"(1,2,3,……)X" represents Max Loading of this stituation is (1,2,3,……) times than Max Loading of Normal(1X) condition.
----------------------------------------------------------------------------------------

Because 1X use 1 set of p/n mos, 2X use 2 set(parallel) of p/n mos, 3X use 3 set of p/n mos…… in layout , which will result in a larger driving strength.

Althrough I ’m clear that gate sizing(width & length, P/N width ratio) determines driving strength,
I'm wonder how determine the gate sizing in Normal(1X) condition that is optimal delay(contain Tphl, Tplh……)， or is optimal power consumption(contain short power, switch power……)， or……


pls help me ！！！

 

[rain_181914]

Pls help and give me some suggestions , I will appreciate with your kindness.

 

[rain_181914]

who can help me

 

[onlymusic16]

who can help me

What is the problem statement? Please Tell clearly.

 

[rain_181914]

A short summary, what conditions decide on normal driving(1X driving strength) in standardcell library?


I don't know whether I have expressed celarly.

 

[onlymusic16]

A short summary, what conditions decide on normal driving(1X driving strength) in standardcell library?


I don't know whether I have expressed celarly.

Drive strength of a cell depends on many factors but i think you are asking if w/l of mosfets play a role in deciding that? Yes, it is an important factor which determines the driving strength of the cell. The lesser the rise/fall transition times (at the output), the more the driving strength.

Hope it helps.

 

[rain_181914]

Thanks for you replying.

I unstandard your viewpoint, but I want to know what detail conditions determine 1 time driving strength. Because standardcell library usually have some kinds of cells(1 time driving strength, 2 times driving strength, and so on) in one type.

How does library(standardcell) designer make the 1 time driving strength cell?
and how to distribute(assign) the propagation delay(cell rise, cell fall), the power consumption and the area.
Above all, gate sizing width ratio(wp/wn) base on 3 aspects(the propagation delay(cell rise, cell fall), the power consumption and the area)[/youtube]

 

[onlymusic16]

Any designer would want to make a cell so that it takes minimum area and power impact with higher speed(lesser delays). This is the starting point for any design.

Design a simple inverter, use a true spice simulator (say hspice) and find out which set of mosfets with w/l give you the best results (as explained above). Say you are getting the best performance but your area is being blown up considerably, discard those values and take smaller values to get the OPTIMUM PERFORMANCE. Its a trade off actually.

Hope it helps!!!

 

[rain_181914]

Base on it, Whether I can think that I catch on a min propagation delay by Wp/Wn width ratio, un, up, and load capacitance/input capacitance ratio. Then make sure a wp or wn to get a trade off condition when Wp/Wn is a fix value ?

But I wonder to know how to make sure a wp or wn, a larger width, a bigger area, a lbetter driving strength.
Furthermore, a changed Wp or Wn will result in a changed input capacitance, so It is difficult to get a minimal propagation delay.

I think I have a lot of threads of an affair, pls help.[/youtube]

 

[rain_181914]

It is so my botttleneck that I can't continue it.

Can Anybody give me some suggestions ?

 

[onlymusic16]

You need to try first, i am sure if you start with a simple inverter and move onto big circuits you will gain a lot of confidence.

Furthermore, i would suggest you to go through 'Logical Effort' concept but read it only after you have designed and characterized a simple inverter.

Start with a ratio of 2:1 and see what exactly this ratio comes out to be in your technology, for a simple inverter. Post your problems here if you find any.

 

[rain_181914]

I tried to run it.

I took a p/n width ratio from library file, then I changed it on the basis of 3 methods below.

1.same wp/wn width ratio, diffetent wp and wn
2.different wp/wn width ratio, wp=constant
3.different wp/wn width ratio, wn=constant

From the result sof 3 methods , I did not summarize a regular pattern and did not know why the wp&wn from .lib file is the best .

I think maybe, I just checked the timing(rising , falling, h to l, l to h, progration) for 3 methods. Because I 'm not sure how I can get a tradeoff value, so I didn't consider power and area together.

 

[Chethan]

Hi,

The wp and wn values of the .lib is decided by many factors. First the standard cell is designed with a fixed architecture. Then all the parameters of the cell like i/p cap/rise time/fall time , setup/hold/removal/recovery for sequential cells , are determined. Then the W's of N and P are varied accrdingly to get an optimum rise/fall/delay etc. So the W's you might see in your library is an optimum values taking into consideration of all the above mentioned parameters.

regards
Chethan

 

[rain_181914]

How to consider all parameters to get a optimal width?

Do i figure out it, by step by step ?

Can you provide an index?

 

[Chethan]

for eg : design an 2 input NAND gate with some reference values of Ws for PMOS and NMOS. Then check out its rise and fall delay. You might find that the difference between them is large. To optimize keep varying the W's of N and P till you get the difference between rise and fall delay close to 5%. this is just an example of how standard cells are optimized for a particular W. follow this procedure for risetime/fall time also. find out its i/pcap and power for this particular W's.

 

[rain_181914]

thank you.

Why the difference is 5% ?
In my opinion, for INV, choose optimal Wp and Wn n when min (tphl+tplh).
for INVCK, choose optimal wp and wn when tphl=tplh.
I think I just consider timing, and how to combine power into it ?

 

[Chethan]

5% is just a standard followed by industry for designing standard cells. You can have your own ratio. But as I said just designing a gate for minimum delay is not always the approach standard cell companies follow. the gate has to be balanced for delay and rise/fall point of view.